This invention relates to a resin sealed semiconductor device in which an LSI chip is connected to a wiring substrate. More particularly, this invention relates to a resin sealed semiconductor device having a bare chip package configuration.
So-called "bare chip package" type semiconductor devices according to the prior art have a construction in which an LSI chip is connected to a wiring substrate by metal bumps, or the like. These semiconductor devices are not free from the problem that a thermal strain develops in the metal bumps due to the difference of coefficients of linear thermal expansion between the LSI chip resulting in the wiring substrate, and the metal bumps undergoing fatigue failure. In order to solve this problem, in a known measure, a gap portion between the LSI chip and the wiring substrate is charged with an epoxy type thermosetting resin containing fine particles such as glass particles (generally called "fillers"). With this arrangement, thermal deformation between the LSI chip and the wiring substrate is restricted so that the thermal stress occurring in the metal bumps can be reduced and connection reliability of the metal bumps can be improved.
Such a measure will be explained by taking JP-A-7-66326 by way of example. This prior art reference illustrates a schematic sectional view of a semiconductor device that is produced by packing a resin at peripheral portions of solder bumps that electrically connect a semiconductor chip such as an LSI chip to a glass substrate. This reference proposes to improve connection reliability of the solder bumps by charging the resin into the gap portion between the semiconductor chip and the glass substrate thereby mitigating deformation resulting from the difference of the coefficients of thermal expansion between the semiconductor chip and the glass substrate.